1. Field of the Invention
The present invention relates to a NAND type dynamic semiconductor random access memory (DRAM) having a unit with a memory-cell group having a plurality of memory cells connected in series. More particularly, the present invention relates to NAND type DRAM including a folded bit line architecture.
2. Description of the Related Art
A high integration density of dynamic random access memories DRAMS has been realized by microfabrication in process technology and device technology. However, microfabrication techniques appear to have reached limits in recent years. Nevertheless, a semiconductor memory unit, referred to as a NAND type DRAM, which included connected in series a plurality of DRAM cells each having 1 transistor/1 capacitor, was recently proposed (ISSCC Digest of technical paper pp. 46-47 (1993)).
In the NAND type DRAM, the large number of contacts to a bit line can be decreased, as compared with a conventional DRAM. For this reason, the area which a memory cell array occupies in a chip can be reduced to enable a high integration density. FIG. 12 shows a circuit diagram of a NAND type DRAM. FIG. 13(a) and FIG. 13(b) show a plan view and a sectional view of the NAND type DRAM, respectively.
A gate-electrode 12 which becomes a word line (WL) is formed on a Si substrate 10 through a gate insulation film 17. A source/drain diffusion layer 11 is formed in the substrate 10 to both sides of the gate electrode 12, and a MOS transistor is thereby formed. A storage node electrode 13 is connected to one of the source/drain diffusion layer 11 of the transistor.
A plate electrode 14 which confronts 13 the electrode 13 is formed over to form a capacitor,e.g., c1, c2, etc. through a capacitor insulation film 18. A one bit memory cell comprises the capacitor including electrodes 13, 14 and the transistor. Here, one of the source/drain diffusion layers 11 is shared with one of the source/drain layers 11 of an adjacent transistor.
In this example, a bit-line (BL) 15 is connected to the one of the source/drain diffusion layers 11 at the respective ends of adjacent four bit memory-cell groups at a bit line contact 16. Thus, a NAND type DRAM having as a unit memory cell groups with a plurality of memory cells connected in series is provided. For this reason, the memory cell can be made small.
In FIG. 12, a reading out/rewriting circuit 19 is connected to the bit lines BL and LBL to read out and rewrite information to the memory cell groups connected to the bit line.
In the illustrated NAND type DRAM, the memory cells exist at the crossing point of the word lines WL and the bit lines BL. The memory cell data is read to all bit lines that intersect the selected word line. For this reason, an open bit line architecture is provided in which a bit line connected to a memory cell array which is arranged at the opposite side of reading out/rewriting circuit 19 is used as a reference bit-line (/BL) and amplifying the potential between the bit line BL and/BL is employed for reading/rewriting.
The open bit line architecture has a disadvantage that the system is very susceptible to noise and soft error in the memory cell array as compared with a folded bit-line architecture which is conventionally used for other DRAM configurations.
FIG. 14 illustrates capacitive coupling between adjacent memory cells and bit lines in a NAND type DRAM.
As shown in FIG. 14, each of bit lines BL0, BL1, and BL2 can receive a coupling noise by the coupling capacitance CBB between adjacent bit lines, when data is read out from a memory cell. Furthermore, the signal read out as the memory cell data causes the potential of the word line WL to change, via the capacitance CWB between crossing bit lines and word lines. This potential change feeds back again and is applied to the bit line BL as another noise. Similarly, the bit line BL receives similar noises through the electrode of a plate or the substrate, etc.
In the open bit line architecture, data is not read out to the reference bit-line, and therefore the above noises are not coupled to the reference bit-line. Accordingly, all noise that occur on a bit line become bit line noise, and the read-out of data cannot be made accurately. Similarly, the open bit line architecture has a disadvantage that soft errors caused by alpha ray which impinge on the BL contact also occur only on one side of a pair of bit lines.
Thus, in the conventional NAND type DRAM, the open bit-line architecture is employed in which data is read to all bit lines connected with the selected word line and the cell array is arranged at one side of the reading out/rewriting circuit 19.
Therefore, a DRAM chip size can be reduced.
However, there is a problem that a NAND type DRAM having a high reliability cannot be realized because of the noises or the soft error experienced in the memory cell array.